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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Monostable Multivibrator
The MC10198 is a retriggerable monostable multivibrator. Two enable inputs permit triggering on any combination of positive or negative edges as shown in the accompanying table. The trigger input is buffered by Schmitt triggers making it insensitive to input rise and fall times. The pulse width is controlled by an external capacitor and resistor. The resistor sets a current which is the linear discharge rate of the capacitor. Also, the pulse width can be controlled by an external current source or voltage (see applications information). For high-speed response with minimum delay, a hi-speed input is also provided. This input bypasses the internal Schmitt triggers and the output responds within 2 nanoseconds typically. Output logic and threshold levels are standard MECL 10,000. Test conditions are per Table 2. Each "Precondition" referred to in Table 2 is per the sequence of Table 1. PD = 415 mW typ/pkg (No Load) tpd = 4.0 ns typ Trigger Inpt to Q 2.0 ns typ Hi-Speed Input to Q Min Timing Pulse Width Max Timing Pulse Width Min Trigger Pulse Width Min Hi-Speed Trigger Pulse Width Enable Setup Time Enable Hold Time PWQmin PWQmax PWT PWHS tset thold 10 ns typ1 >10 ms typ2 2.0 ns typ 3.0 ns typ 1.0 ns typ 1.0 ns typ
MC10198
L SUFFIX CERAMIC PACKAGE CASE 620-10 P SUFFIX PLASTIC PACKAGE CASE 648-08 FN SUFFIX PLCC CASE 775-02
DIP PIN ASSIGNMENT
VCC1 Q Q CEXT EPOS REXT EXT.PULSE WIDTH CONTROL
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VCC2 HIGH-SPEED INPUT N/C TRIGGER INPUT N/C N/C ENEG N/C
1 CExt = 0 (Pin 4 open), RExt = 0 (Pin 6 to VEE) 2 CExt = 10 F, RExt = 2.7 k
LOGIC DIAGRAM
VEE VCC
VEE
6 5 7 10 13 15 REXT E pos
4 CEXT Q 3 VCC1 = PIN 1 VCC2 = PIN 16 VEE = PIN 8
Pin assignment is for Dual-in-Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 6-11 of the Motorola MECL Data Book (DL122/D).
EXTERNAL PULSE WIDTH CONTROL ENEG TRIGGER INPUT HI-SPEED INPUT Q
TRUTH TABLE
INPUT EPos ENeg L L H L L H H H OUTPUT Triggers on both positive & negative input slopes Triggers on positive input slope Triggers on negative input slope Trigger is disabled
2
3/93
(c) Motorola, Inc. 1996
3-172
REV 5
MC10198
TABLE 1 -- PRECONDITION SEQUENCE
1. At t = 0 Apply VIHmax to Pin 5 and 10. Apply VILmin to Pin 15. Ground Pin 4. 2. At t a.) Open Pin 1. b.) Apply -3.0 Vdc to Pin 4. Hold these conditions for ns. 3. Return Pin 4 to Ground and perform test as indicated in Table 2. a.) b.) c.) 10 ns
w 10 ns
0(Gnd) -1.0 -2.0 -3.0 -4.0 -5.0 0 10 Pin 4 Voltage (Vdc)
w 10 ns
w
w10
Pin 1 open
20 t(ns)
30
TABLE 2 -- CONDITIONS FOR TESTING OUTPUT LEVELS (See Table 1 for Precondition Sequence)
VIH max VILA max P1 VIL min P2 VIL min P3 VIHA max VIL min
Pins 1, 16 = VCC = Ground Pins 6, 8 = VEE = -5.2 Vdc Outputs loaded 50 to -2.0 Vdc
Pin Conditions Test P.U.T. 5 10 13 VIL min P1 VIL min P1 VILA max VIHA min VIL min P3 P2 P3 VIH max VIH max VIH max VIH max P2 P3 P1 P1 15 Test P.U.T. 5
Pin Conditions 10 VIHA min VILA max 13 P1 P1 VILA max VIHA min VIL min VIL min P2 P3 VIH max VIH max VIHA min VILA max VIH max VIH max VIH max VIH max VIHA min VILA max P2 P3 P1 P1 P1 P1 15
Precondition VOH 2 VOH 3 Precondition VOL 3 VOL 2 Precondition VOHA 2 VOHA 3 Precondition VOHA 2 VOHA 3 Precondition VOHA 2 VOHA 3 Precondition VOHA 2 VOHA 3 Precondition VOHA 2 VOHA 3
Precondition VOHA 2 VOHA 3 Precondition VOLA 3 VOLA 2 Precondition VOLA 2 VOLA 3 Precondition VOLA 3 VOLA 2 Precondition VOLA 3 VOLA 2 Precondition VOLA 3 VOLA 2 Precondition VOLA 3 VOLA 2
MECL Data DL122 -- Rev 6
3-173
MOTOROLA
MC10198
ELECTRICAL CHARACTERISTICS
Test Limits Pin Pi Under Test 8 5, 10 13 15 5 2 3 2 3 2 3 2 3 0.5 -1.060 -1.060 -1.890 -1.890 -1.080 -1.080 -1.655 -1.655 -0.890 -0.890 -1.675 -1.675 -30C Min Max 110 415 350 560 0.5 -0.960 -0.960 -1.850 -1.850 -0.980 -0.980 -1.630 -1.630 -0.810 -0.810 -1.650 -1.650 Min +25C Typ 80 Max 100 260 220 350 0.3 -0.890 -0.890 -1.825 -1.825 -0.910 -0.910 -1.595 -1.595 -0.700 -0.700 -1.615 -1.615 Min +85C Max 110 260 220 350 Unit mAdc Adc
Characteristic Power Supply Drain Current Input Current
Symbol IE IinH
IinL Output Voltage Output Voltage Threshold Voltage Threshold Voltage Switching Times Trigger Input High Speed Trigger Input Minimum Timing Pulse Width Maximum Timing Pulse Width Min Trigger Pulse Width Min Hi-Spd Trig Pulse Width Rise Time Fall Time (20 to 80%) (20 to 80%) tsetup (E) Logic 1 Logic 0 Logic 1 Logic 0 (50 Load) tT+Q+ tT-Q+ tHS+Q+ PWQmin PWQmax PWT PWHS VOH VOL VOHA VOLA
Adc Vdc Vdc Vdc Vdc
3 3 3 3 3 3 3 3 3 3
2.5 2.5 1.5
6.5 6.5 3.2
2.5 2.5 1.5
4.0 4.0 2.0 10.0 >10 2.0 3.0
5.5 5.5 2.8
2.5 2.5 1.5
6.5 6.5 3.2
ns ns ns ms ns ns
1.5 1.5
4.0 4.0
1.5 1.5 1.0 1.0
3.5 3.5
1.5 1.5
4.0 4.0
ns ns ns ns
Enable Setup Time
Enable Hold Time thold (E) 3 1. The monostable is in the timing mode at the time of this test. 2. CEXT = 0 (Pin 4 Open); REXT = 0 (Pin 6 tied to VEE). 3. CEXT = 10F (Pin); REXT = 2.7k (Pin 6). 4. P1 VIHmax VILmin
MOTOROLA
3-174
MECL Data DL122 -- Rev 6
MC10198
ELECTRICAL CHARACTERISTICS (continued)
TEST VOLTAGE VALUES (Volts) @ Test Temperature -30C +25C +85C Pin Under Test 8 5, 10 13 15 5 2 3 2 3 2 3 2 3 +1.11V tT+Q+ tT-Q+ tHS+Q+ PWQmin PWQmax PWT PWHS 3 3 3 3 3 3 3 3 3 tsetup (E) 3 5 5 3 3 13 15 10 5 13 (4.) 13 (4.) 13 15 15 15 15 Pulse In 13 13 15 Pulse Out 3 3 3 Note 2. Note 3. 3 3 5,10 13 15 5 13 VIHmax -0.890 -0.810 -0.700 VILmin -1.890 -1.850 -1.825 VIHAmin -1.205 -1.105 -1.035 VILAmax -1.500 -1.475 -1.440 VEE -5.2 -5.2 -5.2 (VCC) Gnd 1, 4, 16 1, 4, 16 1, 4, 16 1, 4, 16 1, 4, 16 1, 4, 16 1, 4, 16 1, 4, 16 1, 4, 16 1, 16, 4 1, 16, 4 1, 16, 4 1, 16, 4 +2.0 V 1, 16, 4 1, 16, 4 1, 16, 4 1, 16, 4 1, 16, 4 1, 16, 4 1, 16, 4 1, 16, 4 1, 16, 4 1, 16, 4 1, 16, 4
TEST VOLTAGE APPLIED TO PINS LISTED BELOW VIHmax VILmin VIHAmin VILAmax VEE 6, 8 6, 8 6, 8 6, 8 6, 8 6, 8 6, 8 6, 8 6, 8 6, 8 6, 8 6, 8 6, 8 -3.2 V 6, 8 6, 8 6, 8 6, 8 6, 8 6, 8 6, 8 6, 8 6, 8 6, 8 6, 8
Characteristic Power Supply Drain Current Input Current
Symbol IE IinH
IinL Output Voltage Output Voltage Threshold Voltage Threshold Voltage Switching Times Trigger Input High Speed Trigger Input Minimum Timing Pulse Width Maximum Timing Pulse Width Minimum Trigger Pulse Width Minimum Hi-Spd Trigger Pulse Width Rise Time Fall Time Enable Setup Time (20 to 80%) (20 to 80%) Logic 1 Logic 0 Logic 1 Logic 0 (50 Load) VOH VOL VOHA VOLA
Enable Hold Time thold (E) 3 1. The monostable is in the timing mode at the time of this test. 2. CEXT = 0 (Pin 4 Open); REXT = 0 (Pin 6 tied to VEE). 3. CEXT = 10F (Pin); REXT = 2.7k (Pin 6). 4. P1 VIHmax VILmin
Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained. Outputs are terminated through a 50-ohm resistor to -2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the same manner.
MECL Data DL122 -- Rev 6
3-175
MOTOROLA
MC10198
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS @ 25C
Vin 25 F Coax 5 7 Input TPin 10 Pulse Generator +1.11 V 0.1 F 15 Input Pulse t+ = t- = 2.0 0.2 ns (20 to 80%) 13 VCC1 = VCC2 = +2.0 Vdc Vout 0.1 F Coax
EPos External Pulse Width Control ENeg Trigger Input Hi-Speed Input Q 3
TPout
6 4
RExt CExt
Q
2
50-ohm termination to ground located in each scope channel input. All input and output cables to the scope are equal lengths of 50-ohm coaxial cable. Wire length should be < 1/4 inch from TPin to input pin and TPout to output pin.
0.1 F VEE = -3.2 Vdc
Unused outputs are tied to a 50-ohm resistor to ground.
EPos Trigger Input 50% tT+Q+ PWT tT-Q+ 50%
50% tsetup (E)
tHold(E) 50%
Q
PWQ
High-Speed Trigger Input tHS+Q+ Q PWQ PWHS
MOTOROLA
3-176
MECL Data DL122 -- Rev 6
MC10198
APPLICATIONS INFORMATION Circuit Operation: 1.PULSE WIDTH TIMING -- The pulse width is determined by the external resistor and capacitor. The MC10198 also has an internal resistor (nominally 284 ohms) that can be used in series with RExt. Pin 7, the external pulse width control, is a constant voltage node (-3.60 V nominally). A resistance connected in series from this node to VEE sets a constant timing current IT. This current determines the discharge rate of the capacitor: V IT = CExt T where T = pulse width V = 1.9 V change in capacitor voltage Then: 1.9 V T = CExt IT
PULSE WIDTH ( s)
Figure 2 shows typical curves for pulse width versus CExt and RExt (total resistance includes RInt). Any low leakage capacitor can be used and RExt can vary from 0 to 16 k-ohms. 2.TRIGGERING --The Epos and ENeg inputs control the trigger input. The MC10198 can be programmed to trigger on the positive edge, negative edge, or both. Also, the trigger input can be totally disabled. The truth table is shown on the first page of the data sheet. The device is totally retriggerable. However, as duty cycle approaches 100%, pulse width jitter can occur due to the recovery time of the circuit. Recovery time is basically dependent on capacitance CExt. Figure 3 shows typical recovery time versus capacitance at IT = 5 mA.
FIGURE 2 - TIMING PULSE WIDTH versus CExt and RExt 100
If RExt + RInt are in series to VEE: IT = [(-3.60 V) - (-5.2 V)] / [RExt + 284 ] IT = 1.6 V/(RExt + 284) The timing equation becomes: T = [(CExt)(1.9 V)] / [1.6 V/(RExt + 284)] T = CExt (RExt + 284) 1.19 where T = Sec RExt = Ohms CExt = Farads
10
10 k 3 k
1
500
100
RExt = 0
NOTE: TOTAL RESISTANCE = RExt + RInt 0.1 F
10 10 pF
100 pF
1000 pF 0.01 F CExt - TIMING CAPACITANCE
FIGURE 1 --
FIGURE 3 -- RECOVERY TIME versus CExt @ IT = 5 mA 10 s
4
CExt RECOVERY TIME 1 s
MC10198 7 RInt 284 6 RExt VEE = -5.2 V -3.60 V External Pulse Width Control
100 ns
10 ns
1 ns 10 pF
100 pF
0.01 F 1000 pF CExt - TIMING CAPACITANCE
0.1 F
MECL Data DL122 -- Rev 6
3-177
MOTOROLA
MC10198
3.HI-SPEED INPUT -- This input is used for stretching very narrow pulses with minimum delay between the output pulse and the trigger pulse. The trigger input should be disabled when using the high-speed input. The MC10198 triggers on the rising edge, using this input, and input pulse width should narrow, typically less than 10 nanoseconds.
FIGURE 5 -- PULSE WIDTH versus IT @ CExt = 13 pF
1000
PULSE WIDTH (ns)
100
USAGE RULES: 1.Capacitor lead lengths should be kept very short to minimize ringing due to fast recovery rise times. 2.The E inputs should not be tied to ground to establish a high logic level. A resistor divider or diode can be used to establish a -0.7 to -0.9 voltage level. 3.For optimum temperature stability; 0.5 mA is the best timing current IT. The device is designed to have a constant voltage at the EXTERNAL PULSE WIDTH CONTROL over temperature at this current value. 4.Pulse Width modulation can be attained with the EXTERNAL PULSE WIDTH CONTROL. The timing current can be altered to vary the pulse width. Two schemes are: a. The internal resistor is not used. A dependent current source is used to set the timing current as shown in Figure 4. A graph of pulse width versus timing current (CExt = 13 pF) is shown in Figure 5.
10 0.01 mA
0.1 mA
1 mA
10 mA
IT - TIMING CURRENT
b. A control voltage can also be used to vary the pulse width using an additional resistor (Figure 6). The current (IT + IC) is set by the voltage drop across RInt + RExt. The control current IC modifies IT and alters the pulse width. Current IC should never force IT to zero. RC typically 1 k.
FIGURE 4 --
FIGURE 6 --
4 4 CExt IT MC10198 284 7 6 I IT + IC RExt -5.2 V -3.6 V 7
CExt
IC RC Control Voltage
MOTOROLA
3-178
MECL Data DL122 -- Rev 6
MC10198
5.The MC10198 can be made non-retriggerable. The Q output is fed back to disable the trigger input during the triggered state (Logic Diagram). Figure 7 shows a positive triggered configuration; a similar configuration can be made for negative triggering.
FIGURE 7 --
VEE RExt
VCC
CExt 6 4
E Pos External Pulse Width Control -0.9 V ENeg Trigger Input Hi-Speed Input
Q
Q
MECL Data DL122 -- Rev 6
3-179
MOTOROLA
MC10198
OUTLINE DIMENSIONS
FN SUFFIX PLASTIC PLCC PACKAGE CASE 775-02 ISSUE C
B -N- Y BRK D -L- -M- W D Z
0.007 (0.180) M T L-M U
S
N
S S
0.007 (0.180) M T L-M
N
S
20
1
X V VIEW D-D
G1
0.010 (0.250)
S
T L-M
S
N
S
A Z R
0.007 (0.180) M T L-M 0.007 (0.180) M T L-M
S
N N
S
S
S
H
0.007 (0.180) M T L-M
S
N
S
C
E 0.004 (0.100) G G1 0.010 (0.250) S T L-M J -T-
SEATING PLANE
K1 K F VIEW S 0.007 (0.180)
M
VIEW S
S
T L-M
S
N
S
N
S
NOTES: 1. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635).
DIM A B C E F G H J K R U V W X Y Z G1 K1
INCHES MIN MAX 0.385 0.395 0.385 0.395 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 --- 0.025 --- 0.350 0.356 0.350 0.356 0.042 0.048 0.042 0.048 0.042 0.056 --- 0.020 2_ 10 _ 0.310 0.330 0.040 ---
MILLIMETERS MIN MAX 9.78 10.03 9.78 10.03 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 --- 0.64 --- 8.89 9.04 8.89 9.04 1.07 1.21 1.07 1.21 1.07 1.42 --- 0.50 2_ 10 _ 7.88 8.38 1.02 ---
MOTOROLA
3-180
MECL Data DL122 -- Rev 6
MC10198
OUTLINE DIMENSIONS
L SUFFIX CERAMIC DIP PACKAGE CASE 620-10 ISSUE V
9
-A-
16
-B-
1 8
C
L
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. DIM A B C D E F G H K L M N INCHES MIN MAX 0.750 0.785 0.240 0.295 --- 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 --- 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15 _ 0.51 1.01
-T-
SEATING PLANE
N E F D G
16 PL
K M J
16 PL
0.25 (0.010)
M
M
TB
S
0.25 (0.010)
TA
S
-A-
16 9
P SUFFIX PLASTIC DIP PACKAGE CASE 648-08 ISSUE R
B
1 8
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01
F S
C
L
-T- H G D
16 PL
SEATING PLANE
K
J TA
M
M
0.25 (0.010)
M
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JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 81-3-3521-8315 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298
MECL Data DL122 -- Rev 6 3-181
*MC10198/D*
MC10198/D MOTOROLA

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